Phase synchronism system for a one-way telegraph connection

ABSTRACT

A one-way telegraph system for permitting recurring phase synchronism checks by transmitting at predetermined intervals a definite series of alternate special service and/or idle time signals which form a start signal. This system includes means for transmitting each signal twice separated by a predetermined time interval, three successive registers therefor, means for detecting in the transmitter a certain regularly occurring signal, such as the &#39;&#39;&#39;&#39;line feed&#39;&#39;&#39;&#39; signal, counter means for interrupting traffic for said predetermined interval, means for generating said start signal in said registers and transmitting said start signal during said predetermined interval, and a pulse distributor for controlling all said means.

United States Patent lnventor Herman Da Silva Voorburg, NetherlandsAppl. No. 829,331 Filed June 2, 1969 Patented Assignee Aug. 24, 1971 DeStaat Der'Nederlanden Ten Deze Vertegenwoordigd Door De Directeur-Generaal Der Posterijen Telegrafie En Telel'onie The Hauge, NetherlandsJune 6, 1968 Netherlands Priority PHASE SYNCHRONISM SYSTEM FOR A ONE-WAYAND- FLIP- GATES FLOPS {TAPE READER l L l l l l I l I l l CODE CONVERTERPrimary Examiner-Kathleen H. Claffy Assistant Examiner-Thomas W. BrownAttorney-Hugh Adam Kirk ABSTRACT: A one-way telegraph system forpermitting recurring phase synchronism checks by transmitting atpredetermined intervals a definite series of alternate special serviceand/or idle time signals which form a start signal. This system includesmeans for transmitting each signal twice separated by a predeterminedtime interval, three successive registers therefor, means for detectingin the transmitter a certain regularly occurring signal, such as theline feed" signal, counter means for interrupting traffic for saidpredetermined interval, means for generating said start signal in saidregisters and transmitting said start signal during said predeterminedinterval, and a pulse distributor for controlling all said means.

FEEDBACK SHIFT SHIFT REGISTER II REGISTER III REGISTER 1 CLOCK PULSES(I00 H1) DISTRIBUTOR PATENTED AUG24|97| 8,601. 539

sum 1 OF 3 CHARACIER TRANSPORT TRAFFIC V' SIGNALS TIME ---n q- 1 1INTERVAL TD START SIGNAL a E L a i I BEPETITIIJN (2nd wmsm FIRST TBANSM.

FIG.1

INVENTUR. HERMAN DA SILVA BYW ATTOR NEY PATENIEDAus24|91| 3,691, 539

sum 2 OF 3 mOkDmEhma Yaw/50mm.

ATTORNEY BACKGROUND OF THE INVENTION Such a system is known from thepublished Netherlands Pat. application No. 6604449 made by theapplicant. This system provides a method of establishing synchronismbefore the transmission of traffic. It is possible, however, that areceiver is switched on at a moment when traffic is going on already. Inthe system according to the Netherlands patent application a receivercannot enter into synchronism when traffic transmission [S111 progress.

SUMMARY OF THE INVENTION The invention relates to a system fortransmitting information in a one-way telegraph connection which allowsa receiver to enter into synchronism during traffic transmission. Forthis purpose the system is so arranged that during traffic transmission,phasing can be effected by transmitting a start criterion at regularintervals, such as at 'the beginning of a fresh line.

It can further be so arranged that, if in the transmitter the supply ofthe line feed signal NR" is detected, the supply of fresh trafficsignals to the transmitter is interrupted for the duration of aspecified number of signal cycles for a start criterion of a number ofspecial service l-signals alternating with an equal number of idle timea-signals to be generated and transmitted, after which the line feedsignal NR is transmitted.

BRIEF DESCRIPTION oF THE VIEWS The above-mentioned and other features,objects, and advantages. and-a manner of attaining them are describedmore specifically below by reference to an embodiment of this inventionshown in the accompanying drawings, wherein:

FIG. 1 is a schematic time diagram of the signals involved in theoperation of the system according to this invention;

FIG. 2 is a schematic block wiring diagram of a transmitter circuitaccording to a preferred embodiment of this invention;

FIG. 3 discloses a plurality of pulse waveform diagrams indicating thetimes at which the various pulses mentioned in the description ofFIG. 2occur; and

FIG. 4 is a table of the blocks and other symbols used in the diagram ofFIG. 2 together with descriptions of their functions.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Beside the middlecolumn of the time diagram of FIG. are indicated the traffic signals A,"B," C etc. and the line feed signal NR" supplied in succession to thetransmitter. This supply takes place at a rate of 50 bauds; while thetransmission speed is double this speed. i.e. 100 bauds, so that everysignal is transmitted twice in this embodiment. Along thetransmission'or right-hand column in FIG. 1, the signals transmitted forthe first time are indicated atthe left, and the signals transmitted forthe second time (repeated signals) are indicated at the right. The timedifference between the two transmissions is designated by interval TD."

For the receiving stations it is not only important that they start inthe correct character phase, but also that they start in such a way thatthe first signals and the repeated signals fall at the correct places inthe receiving distributors. This is essen' tial, because the receiversare so arranged that the first signal received (at the left of thetransmission or right-hand column in FIG 1) is tested first. If thisfirst signal is found incorrect, it is rejected, but if found correct itis stored in order to be printed after the reception of the relevantsecond transmission (repetition) of that signal. If the secondtransmission (repetition) of that signal is found correct, but the firstis not, the

second will be printed. If the two or both signals are incorrect,

' no correction is possible and an error symbol is printed. Thus theinterchange of first and second transmission signals can be disastrous.

The start signal ensures that at the start the special service signal S1or I-signal is recorded in the direct (first) signal location, and theregular idle time a signal in the repetition (second) signal location.For this purpose the receivers are equipped with a receiver shiftregister through which every signal received is shifted at the rate ofbauds. When this register is entirely occupied by the I-signal, aprovisional start will be made and a test will be carried out on thenext signal, in order to ascertain whether or not it is an a-signal. Ifit is, the start will be considered as correct and definitive, but if itis not, the receiver will fall back to standby.

Thus, the service signals I-a-I-a, forming the start signal," aretransmitted in an uninterrupted alternation when no information istransmitted, so that every receiver has an ample opportunity to get intophase. Nevertheless there will be receiving stations which receive nosignals until the transmission of information is in progress or whichhave lost phase. Consequently, these stations would be deprived of allfurther information. Now according to this invention this start signalis repeated at regular intervals, for which the line feed signal NBihasbeen chosen as criterion. This signal NR, or the bit combination 01000,is bound to occur at least once is every 64 signals, which is themaximum length of a line in a teleprinter. Now the transmitter isprovided with means, namely a line feed signal, for interrupting thetraffic supply for the duration of four signals in order to transmitthis foursignal or character cycle start signal In FIG. I this is in-.dicated by hatching along the (character transport or signal supply,left-hand column) at the dotted arrows 1" through 4, During thisinterruption of the traffic supply only two of the'four signals of thestart signal sequence are effective, because the first two SI orI-signals are followed by the repeated signals (in the example in FIG.1: B and C and thereafter followed by the a-signal. Thus after the four51" or l-signa1s are transmitted, the signal (NR) is transmitted.

In the transmitter represented by the block diagram of FIG. 2, thecontacts 1 through 5 of the tape reader TR pass the information suppliedby the five-hole tape to the AND gates G1 through G5; a l-bit passing asa potential and a 0 as a potential. These AND gates G1 through G5controlled by P3- pulses occurring at instants indicated in FIG. 3, putthe flipflops A through E in the l-state or the O-state in accordancewith the information read. The outputs of these flip-flops A-E controlthe code converter CC consisting of logic circuits as may be consideredwell known for converting a five-unit Baudeau code into a seven-unitbalanced or constant ratio code, such as in US. Pat. No. 2,518,405. Viathe AND gates G6 through G12 controlled by P4-pulses, the outputs ofthis code converter CC control the flip-flops IA through 16, notably insuch a manner that these seven flip-flops IA-IG exhibit the l-Oconfiguration of the relevant seven-bit constant-ratio signal. Theseflip-flops are arranged as a shift register I, so that under the controlof Pl-pulses occurring seven times at intervals of 10 (milliseconds),the information stored in flip-flops 1A through 16 is led via the ANDgates 28 through 33, conductor 100, and the OR gate 41 to the keyingflip-flop Z, which transmits the sevenbits information for the firsttime.

The seven Pl-pulses are immediately followed by seven P2- pulses spacedby the same intervals as the P1-pulses with the pulse P2/l occurring 10ms. after the pulse Pl/7, see FIG. 3. Now, via the AND gates 34 to 40,the P2 pulses shift the information from the shift register IIIAIIIGthrough the OR gate 41 to keyer Z. Thus the keyer flip-flop Z keysalternately a signal from the shift register I and from the shiftregister [11, so that the first transmission of a signal takes placefrom the shift register I and the second from the shift register III.

After the transmission of the register I information, the contents ofthe shift register I are transferred via the AND gates 13 through 19,controlled by P4-pulses, to the storage register 11. At the same timethe information contained in the storage register 11 is transferred viathe AND gates 20 through 26, also controlled by the same P4-pulses, tothe shift register 111. Furthermore this same P4-pulse transfers thefresh information from the code converter CC via the AND gates 6 to 12through the first shift register I. The P4-pulse appears once every 140ms. so that every 140 ms. the information is shifted from one registerto the next register. When, under the control of Pl-pulses, shift theregister I bit-information is transmitted successively to the keyer Z,and the information delivered at flip-flop IA is written back into theregister again at flip-flop 16, via conductors 100 and 101 and the ANDgate 52, so that after seven Pl-pulses the shift register I contains theoriginal information again. Thus this first shift register I is also afeedback shift register.

Once every 140 ms. the flip-flop S is put in the l-state for theduration of 20 ms. (see also FIG. 3) and a relay connected to it isenergized to close the contacts for 20 ms. thus effecting theenergization of the transport magnet M for transporting the tape throughthe tape reader TR.

When the tape reader TR is switched off, i.e. when its gcontact is open,a negative potential is applied via register R6 and conductor 102 to theinverter 44, as a result of which a positive potential appears at theOR-gate 43, so that the flip-flop PD assumes the l-state under thecontrol of a P2/7-pu1se applied to the AND gate 45, The flipflop PD thenapplies a positive potential to the AND gate 47, so that this gate 47,under the control ofthe PS-pulse, puts the fiip-flops 1B, IC, IF and [Gin the l-state via the diodes D1 through D4, and the flip-flops IA, IDand IE in the -state via the diodes D5, D6 and D7. Irrespective of theformation the flip-flops have just assumed via the code converter, thePS-pulse puts these flip'flops 1A1G into the configuration 01 10011,which is the bit combination for the special service signal 81" or Thesame PS-pulse puts the flip-flop PR in the l state via the gate 48. Thenext P4-pulse transfers this special service signal 1" or S1 from theregister I to the register II. But since flip-flop PR is in the 1-state, the next P5-pulse immediately following the P4-pulse, will changethe combination for signal 51" just set up in the register 11. into thebit-combination 1111000 for the idle time signal tf via the diodes D8,D9, D and D11. Then at the next P-S-pulse this combination istransferred to the register 111, so that when this register 111 is readout by P2 pulses, the bit-combination for idle time is transmitted.

So if the tape reader TR is switched off permanently, fliptlops PD andPR will stay in the l-state and the idle time trans; mission will be asfollows: signal 1, "a," signal I, a," etc. The switchingin ofthe tapereader causes the negative potential at the inverter 44 to disappear andvia this circuit the gate 45 will become inactive. On the other hand thepositive potential now existing is applied to the gate 46, so thatflip-flop PD takes the O-state as does the flip-flop PR at the nextPS-pulse, so that from then on the contents ofthe register 1 and II areno longer changed into the signals 1" and a.

When the tape reader reads the line feed signal NR, the flip-flops A, C,D and E take the O-state, whereas flip-flop B assumes the l-state.Because, as will be seen later, the potential at terminal a of thecounting circuit T07 is positive too, this signal NR" bit combinationcauses the gate 50, controlled by the pulse P2/l, to deliver a pulsewhich deblocks (starts) this counting circuit T07 at its inputterminals.

When deblocked at terminal .r this counting circuit T07 pass through thestates 0 to 7 can pass through the states 0 to 7 under the control ofthe Pl/l-pu1se, which appears once every 140 ms. The output terminal ais positive in the counting state 0, so the gate 50 is only conducting,when the counter T07 is at normal and the "line feed bit combination"NR" is sup plied. The output terminal I: is positive in the countingstates 1. 2, 3 and 4 and puts the llip-llop PD in the l-state fromterminal it via the OR gate 43 and the gate 45, just as if the tapereader TR were switched off. This positive b-potential is also led viathe inverter 51 as a negative potential to the gate 46, so that thisgate is blocked. After 4x140 ms. the flip-flop PD is enabled to assumethe O-state again via the closed g-contact. For the duration of the fourperiods (character cycles) the flip-flop S is blocked via the gate 42,so that for four more character cycle times there appears no transportpulse at the tape reader TR. After the first four cycles of idle timesignals, traffic will continue by first the transmission of the linefeed signal NR" For another four character cycles, i.e. until T07 hasfinished counting to 0, the gate 50 cannot become active. This meansthat possible further line feed combinations will have no effect onflip-flop PD and, consequently, will not cause an idle time interval, sothat the transmission of another start signal" or the special four idletime signal sequence is prevented. Suppose a line feed bit combinationhas entailed the start of the counter T07 and a consequent idle timeinterval preceding the transmission of the relevant line feed signal. Inthat case a next line feed signal cannot start the counter anew andinitiate an idle time interval until the counter has finished countingand has been restored to normal.

If desired, the fourfold transmission of the signal I/signal acombination to form a start signal as well as the time between whichsuch start signals can be repeated, can be varied by adjusting theintermediate and maximum counting states of the counting circuit T07.

By the system according to this invention the most dependabletransmission possible is achieved via one channel and with anunambiguous and rapid phasing. In the case of correct (undisturbed)reception, phasing is effected in about half a second.

While there is described above the principles of this invention inconnection with specific apparatus, it is to be clearly understood thatthis description is made only by way of example and not as a limitationto the scope of this invention.

1 claim:

1. A phase synchronism system for a one-way telegraph system comprisingat the transmitter station:

va. means (TR) for reading successive telegraph signals into the systemfor transmission,

. means (1, 11, 111,) for recording three successive signals,

. means (50) for detecting a predetermined signal from said readingmeans,

d. means (T07) for interrupting said reading means for a predeterminednumber of signal cycles controlled by said detecting means,

means (Dl-Dll) for generating two different service signals in saidrecording means controlled by said detecting means, and

. means for alternately transmitting said two generated service signalsduring said predetermined number of signal cycles that said readingmeans is interrupted to produce a start signal by which synchronism at areceiver station can be established.

2. A system according to claim 1 wherein said recording means includesthree registers (IAIIlG) for each bit of said three signals.

3. A system according to claim 2 wherein said three registers aresuccessively a feedback shift register (IA-1G), a transferring register(IIAIIG),

4. A system according to claim 3 wherein said transmitting means readssuccessively said signals from said feedback shift register and saidshift register.

5. A system according to claim 1 including a code-converting means (CC)for converting the signals from said reading means into a constant ratiocode before they are recorded in said recording means.

6. A system according to claim 1 wherein said predetermined signaldetected in said detecting means comprises a recurring signal in one-waytelegraph code signals.

7. A system according to claim 6 wherein said predetermined signalcomprises a teleprinter control signal.

8. A system according to claim 7 wherein said teleprinter control signalis the line feed signal.

9. A system according to claim 1 wherein said generating means comprisesa plurality of pulse-controlled diodes connected to said recordingmeans.

13. A system according to claim 1 wherein said reading means comprises atape reading means.

14. A system according to claim 1 wherein said means for interruptingsaid reading means comprises a counter circuit for counting saidpredetermined number of signal cycles.

15. A system according to claim 1 wherein one of said service signals isan idle time signal.

P0405) UNITED STATES PATENT OFFICE CERTIFICATE OF CORRECTION Patent 3,601,539 Dated Aug. 24, 1971 lnventorficag) Herman Da SILVA It iscertified that error appears in the above-identified patent and thatsaid Letters Patent are hereby corrected as shown below:

Column 1, line 53, after "Fig. insert l Column 2, line 25, .1

" "NB" should read "NR" line 26, "is" second occurrence, should read inline 31, after "signal" insert a line 32, after "the" delete the line33, after "column" delete the line 58, after "10" insert ms Column 3,line 5, "to" should read through line 6, "through" should read to line9, shift the" should read the shift line 21, 'gcon." should readq-conline 54, "register" should read registers line 59, "T07" shouldread T07 line 62, 'T07" should read T07 line 63, "T07 pass" should readT07 line 64, delete "through the states 0 to 7" line 67, "T07" shouldread T07 Column 4, line 1, "g-contact" should read q-contact line 7,after" "NR" inserta and "T07" should read T07 line 23, "T07" should readT07 line 41, (claim 1), "(T07)" should read (T07) line 57, (claim 3),after the insert and a shift register (IlA 111G).

Signed and sealed this 2nd day of May 1972.

(SEAL) Attestt ROBERT GOTTSCHALK EDWARD M'FLETCHERJR. Commissioner ofPatents Attesting Officer

1. A phase synchronism system for a one-way telegraph system comprisingat the transmitter station: a. means (TR) for reading successivetelegraph signals into the system for transmission, b. means (I, II,III,) for recording three successive signals, c. means (50) fordetecting a predetermined signal from said reading means, d. means (T07)for interrupting said reading means for a predetermined number of signalcycles controlled by said detecting means, e. means (D1-D11) forgenerating two different service signals in said recording meanscontrolled by said detecting means, and f. means for alternatelytransmitting said two generated service signals during saidpredetermined number of signal cycles that said reading means isinterrupted to produce a start signal by which synchronism at a receiverstation can be established.
 2. A system according to claim 1 whereinsaid recording means includes three registers (IA-IIIG) for each bit ofsaid three signals.
 3. A system according to claim 2 wherein said threeregisters are successively a feedback shift register (IA-IG), atransferring register (IIA-IIG),
 4. A system according to claim 3wherein said transmitting means reads successively said signals fromsaid feedback shift register and said shift register.
 5. A systemaccording to claim 1 including a code-converting means (CC) forconverting the signals from said reading means into a constant ratiocode before they are recorded in said recording means.
 6. A systemaccording to claim 1 wherein said predetermined signal detected in saiddetecting means comprises a recurring signal in one-way telegraph codesignals.
 7. A system according to claim 6 wherein said predeterminedsignal comprises a teleprinter control signal.
 8. A system according toclaim 7 wherein said teleprinter control signal is the ''''line feed''''signal.
 9. A system according to claim 1 wherein said generating meanscomprises a plurality of pulse-controlled diodes connected to saidrecording means.
 10. A system according to claim 1 wherein saidtransmitting means includes a keyer (Z) and a distributor means forgenerating pulses (P1, P2) for transferring said signals from saidrecording means to said keyer.
 11. A system according to claim 10wherein said pulses alternately transmit signals from the first and thethird recording means.
 12. A system according to claim 10 wherein saiddistributor is controlled by clock pulses.
 13. A system according toclaim 1 wherein said reading means comprises a tape reading means.
 14. Asystem according to claim 1 wherein said means for interrupting saidreading means comprises a counter circuit for counting saidpredetermined number of signal cycles.
 15. A system according to claim 1wherein one of said service signals is an idle time signal.